Semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) have been used in power electronics applications due to their appreciable current carrying and off-state voltage blocking capability with low on-state voltage drop. In terms of industrial applications, Power MOSFET devices are commonly used in many electronics fields such as portable electronics, power supplies, telecommunications and more particularly in many industrial applications relating to automotive electronics.
Conventionally, a power MOSFET has a vertical oriented four-layer structure of alternating p-type and n-type doping. For instance, the n+pn-n+ structure is termed enhancement mode n-channel MOSFET. By applying a voltage higher than a threshold level, which biases the gate positive with respect to the source, an n-type inversion layer or channel will be formed under the gate oxide layer thus forming a connecting layer between the source and the drain regions and allowing a current to flow. Once the device is turned on, the relation between the current and the voltage is nearly linear which means that it behaves like a resistance. The resistance is referred to as the on-state resistance.
High cell density vertical insulated gate FET (IGFET) are preferred because of their low on-state resistance per unit area compared to standard density insulated gate FET devices (typically in the order of 155,000 cells/cm2). Their lower on-state resistance provides higher current capability.
Different high cell density vertical IGFET configurations already exist. U.S. Pat. No. 6,144,067 describes a power MOSgated device with a strip gate poly structure to increase channel width while reducing the gate resistance. As is shown in FIG. 1, the cell structure (102) disclosed therein consists of a base having two narrow oppositely directed extensions (100) from a central laterally enlarged contact section (101). Each cell has connections between strips and longer sections of strips that are closely spaced and wherein these closely spaced strips are employed to reduce the RDSON of a given die. This “Stripe Cell” combination provides a higher breakdown voltage behaviour from the Stripe layout and a reduced RDSON from the Cell layout. However, the RDSON though reduced can still be improved with the increased channel density.
In two other international patent applications WO 01/31711 and WO 01/31709, a semiconductor device uses a single continuous base region (140) with an undulating structure (180) as is shown in FIG. 2. Both devices implement a single well region made by a layout where either the gate layer (134) substantially surrounds the base region (140), or the base region, which is composed of a plurality of branches, substantially surrounds the gate layer of the transistor. By using this undulating structure (180) of the base region, the channel density is improved and thus on-state resistance can be lowered. However, by using another type of structure of the base region which does not require the use of gate feeds that link groups of cells to each other, it is possible to increase the channel density and to lower the on-state resistance as will be shown in the present invention.
U.S. Pat. No. 5,703,389 relating to a vertical IGFET configuration having low on-state resistance describes a stripe configuration or arrangement wherein the stripe regions (31) have a non linear shape that leads to an increase of the channel density as shown in FIG. 3. Those non-linear stripes also improve breakdown voltage characteristics not only compared to individual cell design, which is another type of IGFET configuration, but also compared to IGFET configuration with straight stripes design. As a matter of fact, non-linear stripe configuration according to U.S. Pat. No. 5,703,389 provides a cell density on an order of 1.4 million cells/cm2 and an on-state resistance that is on the order of 25% lower than typical individual cell designs and 35% lower than typical straight or linear stripe designs. Conversely, straight stripe arrangement has a cell density on an order of 700,000 cells/cm2, lower than the cell density of the individual cell configuration which is on an order of 930,000 cells/cm2, and therefore has a breakdown voltage that is 10%-15% higher than individual cell arrangement. A lower cell density results in lower channel density and contributes therefore to higher on-state resistance in IGFET devices.
Other examples of power semiconductor devices are described in U.S. Pat. Nos. 4,823,176 and 5,399,892 and Japanese patent specification 01 238173.
According to the above-mentioned prior art, the notion of cell density is assimilated to the notion of channel density. As a matter of fact, the channel density should be defined as the ratio between the perimeter of the source region and the surface of the cell active area. Usually, the lower the size of the cells, the higher is the ratio, and thus the channel density. Therefore, many improvements of the MOSFET devices consist in reducing the size of the cell region. However, beyond a certain limit the ratio is decreased and the channel density reduced.
These different configurations aim at increasing the channel density thereby providing a vertical IGFET having a low on-state resistance.
A second problem that is pertaining to the problem of increasing the channel density is the improvement of the breakdown voltage. As in the case of some of the previously mentioned patents, the present invention also addresses this breakdown voltage problem.
Typically, the manufacturing of a MOSFET device needs to address the electrical isolation issue so that each base cell region is electrically isolated in an epitaxial layer. Ideally, all base regions should be at the same electrical potential in order to get a good snap back immunity while improving the breakdown voltage, likewise increasing the unclamped inductive switching (referred to as UIS) capability.
Because of the required minimum optical base cell shrinking process for lowering RDSON, it is not so straightforward to manufacture uniform cell structures across the entire MOSFET. Consequently, during the OFF state, and at lower current density, the snap back phenomenon can take place, which dramatically reduces the breakdown voltage behaviour. However, even if the breakdown voltage yield is impacted which consequently increases the final manufacturing cost, the reliability of the tested good devices is not fully guaranteed. There is a risk of transistor failure for higher current density caused by the base cells during UIS testing.
UIS behaviour is associated with a parasitic NPN bipolar transistor phenomenon which appears in the source/body/drain structure. It is common practice to measure the ruggedness of a MOSFET device by characterizing its UIS behaviour. Therefore, in order to reduce the risk of transistor failure during momentary overloads, improvements should be implemented in the Power MOSFET design to enable to dissipate energy while operating in the avalanche condition. However even if the P+ Body region is doped and located close to the beginning of the channel in such a way that the body resistor is dramatically reduced and provides a good immunity against a drop in tension which could activate the parasitic bipolar transistor, and lead to the device failure, it is still necessary to make sure that all individual cells structure are uniform within the entire MOSFET device.
Therefore, a need exists for a power semiconductor device that provides an improved channel density, while not degrading its breakdown voltage, and having a good electrical contact to a unique base region so as to guarantee the high energy capability (UIS).
In term of method for manufacturing a semiconductor device, in a conventional power MOSFET process, photo-masking steps are required to produce a device. These steps include an active-area masking step where a thick field oxide region is left around the periphery of the device, 1 or 2 optional masking steps to provide a polysilicon temperature sensing device, a base masking step, a first blocking mask for forming the source regions, a contact mask, a metal mask and an optional final passivation mask.
It is far from straightforward to reduce the number of masking steps which can be used for every type of configuration. One has to adopt the manufacturing process according to the type of configuration of the cells. In the present case, the manufacturing process has to deal with the step of merging the body cells that will be described in more detail below.